The present invention relates to methods for fabricating semiconductor devices including multilayer interconnection and semiconductor devices fabricated by the fabrication methods.
Recent remarkable progress of semiconductor processing technology has enabled significant size reduction and high integration of interconnection or devices, so that the performance of ULSI has been enhanced. With increased integration degree of interconnection, signal delay in the interconnection has come to determine operation speed of devices. In ULSI in 0.25-μm generation or later generation, attempts to use materials having low dielectric constants, SiOC containing organic substances or organic materials for interlayer insulating films have been made to date. However, these materials have drawbacks in hygroscopicity or heat resistance, and thus it is difficult to establish processes using these materials.
To reduce a delay between interconnections, which is a delay having an especially large influence, a technique for reducing the relative dielectric constant between the interconnections by intentionally providing voids (hereinafter, referred to as air gaps) formed by air (ε=1.0) between interconnections in an insulating material has been proposed. As a method for forming air gaps in a copper interconnect structure, a method in which an insulating film existing between buried interconnections is removed by etching and then another insulating film is deposited is proposed (see, for example, “A Novel SiO2-Air Gap low-k Copper Dual Damascene Interconnect” T Micro electronics V. Arnal et. al., p. 71, 2000 Advance Metallization).
Hereinafter, a method for forming air gaps in a copper interconnect structure will be described with reference to FIGS. 11A through 11D and FIGS. 12A through 12C. FIGS. 11A through 11D and FIGS. 12A through 12C are cross-sectional views of main portions showing a method for forming air gaps in a copper interconnect structure.
First, as shown in FIG. 11A, a first insulating film 10 is deposited over a semiconductor substrate (not shown) on which a semiconductor active device is formed, and then recesses are formed in the first insulating film 10. Subsequently, first barrier metal films 11 are formed on the bottoms and walls of the recesses in the first insulating film 10, and then first interconnections 12 made of copper films are formed so that the recesses are filled therewith.
Next, as shown in FIG. 11B, to prevent peeling of the first interconnections 12 and diffusion of copper forming the first interconnections 12, a liner insulating film 13 is deposited over the first insulating film 10 and the first interconnections 12.
Then, as shown in FIG. 11C, a resist pattern 14 is formed on the liner insulating film 13 by lithography. The resist pattern 14 has an opening pattern with which only portions of the first insulating film 10 located between the first interconnections 12 are removed. The resist pattern 14 is used to form interconnection-to-interconnection gaps between selected ones of the first interconnections 12 and serves as a mask for exposing only regions between the selected first interconnections 12.
Thereafter, as shown in FIG. 11D, dry etching is performed using the resist pattern 14 as a mask to etch the liner insulating film 13 and the first insulating film 10, thereby forming interconnection-to-interconnection gaps 15 between the first interconnections 12.
Subsequently, as shown in FIG. 12A, a second insulating film 17 is deposited over the interconnection-to-interconnection gaps 15 between the first interconnections 12 and the liner insulating film 13, thereby forming, between the first interconnections 12, air gaps 16 whose tops project above the liner insulating film 13. The use of a film having a low coverage rate and poor burying performance as the second insulating film 17 eases formation of the air gaps 16.
Then, as shown in FIG. 12B, etching is performed so that in the second insulating film 17, a connecting hole 17a in which the surface of one of the first interconnections 12 is exposed is formed and then a interconnect trench 17b is formed. In this case, a dual damascene process in which the connecting hole 17a is formed before the interconnect trench 17b is used.
Thereafter, as shown in FIG. 12C, a barrier metal film, a seed film and a plating film are deposited in this order over the second insulating film 17 including the connecting hole 17a and the interconnect trench 17b, and then excessive portions of the barrier metal film, the seed film and the plating film extending off the connecting hole 17a and the interconnect trench 17b are removed by metal-based CMP, thereby forming a via 18 and second interconnections 19. In this manner, a double-layer interconnect structure made of the first interconnection 12 and the second interconnection 19 is formed.
With the foregoing process steps, a semiconductor device including a multilayer interconnect structure in which the air gaps 16 are formed between the first interconnections 12 made of copper films is fabricated. The relative dielectric constant of the air gaps 16 made of air is about ¼ of that of the first insulating film 10. The air gaps 16 reduce the capacitance between adjacent ones of first interconnections 12. Accordingly, a signal delay between the adjacent first interconnections 12 is suppressed, thus implementing a semiconductor device in which an operation margin is large and malfunction is less likely to occur. In addition, conventional interconnection materials can be used, so that cost reduction is achieved.